circuit performance造句
例句與造句
- aerospace series-circuit breakers-test methods-short-circuit performance
航空航天系列.斷路器.試驗方法.短路性能 - aerospace series-circuit breakers-test methods-part 305 : short-circuit performance
航空航天系列.斷路器.試驗方法.第305部分:短路性能 - capacitors for use in tubular fluorescent and other discharge lamp circuits performance requirements
管形熒光燈和其他放電燈線路用電容器性能要求 - aerospace series-circuit breakers-test methods-part 305 : short-circuit performance; german and english version en 3841-305 : 2004
航空航天系列.斷路器.試驗方法.第305部分:短路性能 - the image collecting forepart has the feature of hardware circuit performance reliable and technics advanced and it adopts the technique of paste and four-layer printed circuit
該圖像采集前端具有硬件電路性能可靠，工藝先進(jìn)等特點，并采用了貼片和四層電路印制板技術(shù)。 - It's difficult to find circuit performance in a sentence. 用circuit performance造句挺難的
- in the design process of hardware i studied in depth the a / d sampling circuit performance indicators and related test methods, while providing guidelines on design of the high-speed pcb circuit
另外,在硬件設(shè)計過程當(dāng)中,深入的研究了a/d采樣電路的性能指標(biāo)和相關(guān)測試方法,同時給出了高速pcb電路設(shè)計注意事項。 - such as harmonic distorted in front analog circuit, sample clock shaking, analog power and the noise in ground plane etc . some suggestion of circuit design is given to improve high-speed a / d circuit performance
在高速模數(shù)轉(zhuǎn)換電路的應(yīng)用設(shè)計中地電源供電設(shè)計、模數(shù)地平面設(shè)計、采樣時鐘設(shè)計等方面提出一些具有指導(dǎo)性的意見。 - and it is commonly regarded as fault-free when the comparative deviation of component parameters are within 5 % of the nominal value, while in practical operations the allowance range could be set flexibly according to different requirements for the circuit performance
通常認(rèn)為元件參數(shù)的相對偏差絕對值在標(biāo)稱值的5%范圍內(nèi)為無故障,但實際上元件的容差是可以根據(jù)對電路性能的不同要求而靈活設(shè)定的。 - it was satisfied for performance testing of high-speed a / d circuit in the project assess the factors of reducing a high speed a / d circuit performance were found out, such as harmonic distorted in front analog circuit, . sample clock shaking, analog power and the noise in ground plane etc
并在試驗測試的基礎(chǔ)上找出了影響高速模數(shù)轉(zhuǎn)換電路轉(zhuǎn)換性能的幾個主要的因素，即：前端運放電路諧波失真、采樣時鐘抖動、模數(shù)電源及共地噪聲串?dāng)_等。 - in order to improve the circuit performance and reliability, the considerations of increasing influence of parasitic effects resulted from interconnect crosstalk and delay as well as the electromigration and power consumption drive the introduction of copper and low-k dielectric
為了提高電路性能及可靠性，并對連串?dāng)_及延遲引起的互連寄生效應(yīng)影響的增長，電遷徙和功率損耗等方面進(jìn)行綜合考慮，刺激了低電阻率銅和低介電常數(shù)介質(zhì)的發(fā)展。 - because of the reuse of some building blocks, such as adders and registers in fft processor, and the regularity of the circuit structure, the test scheme can be implemented at ? speed and in parallel without circuit performance degradation, and with minimal additional hardware and area overhead
由于處理器中一些加法器、寄存器的再利用，以及電路結(jié)構(gòu)的規(guī)則性，因而只需最少的額外硬件、面積開銷即可真速、并行地實施該測試方案而不會降低電路性能。 - abstract : based on the principle of the neuron mos device, a novel matched filter structure which is easily realized by neuron mos is presented and the details of circuit performance is analyzed . compared to the conventional structure, the number of circuit elements is decreased greatly for the same function . the test chip is fabricated in 0.35 m process, and the measured result shows that the system structure is feasible and effective
文摘:在神經(jīng)元mos基本工作原理的基礎(chǔ)上,提出了一種新型的匹配濾波器結(jié)構(gòu),并對具體電路進(jìn)行了分析.與傳統(tǒng)的匹配濾波器相比,具有結(jié)構(gòu)簡單的優(yōu)點,大大減少了器件數(shù)目.最后給出了測試芯片的結(jié)果,驗證了電路的可行性 - and the ways to optimize the circuit architecture, minimize the circuit nonidealities and improve the circuit performance are analyzed combined with the characteristics of the modulator architecture . based on it, the switched-capacitor integrator, class a amplifier, nonoverlap clock, voltage reference, comparator, feedback dac have been designed . in the end, the layout design is shown
調(diào)制器采用全差分開關(guān)電容電路實現(xiàn),并根據(jù)系統(tǒng)結(jié)構(gòu)特點就如何優(yōu)化電路結(jié)構(gòu)、克服電路中存在的非理想特性、提高電路性能作了具體分析,在此基礎(chǔ)上完成了開關(guān)電容積分器(開關(guān)、電容、運算放大器)、參考電壓源、比較器、兩相非交疊時鐘、反饋dac等模塊的電路結(jié)構(gòu)和參數(shù)設(shè)計。 - abstract : a new clock-driven eco placement algorithm is presented for standard-cell layout design based on the table-lookup delay model . it considers useful clock skew information in the placement stage . it also modifies the positions of cells locally to make better preparation for the clock routing . experimental results show that with little influence to other circuit performance, the algorithm can improve permissible skew range distribution evidently
文摘:提出了一種新的時鐘性能驅(qū)動的增量式布局算法,它針對目前工業(yè)界較為流行的標(biāo)準(zhǔn)單元布局,應(yīng)用查找表模型來計算延遲.由于在布局階段較早地考慮到時鐘信息,可以通過調(diào)整單元位置,更有利于后續(xù)的有用偏差時鐘布線和偏差優(yōu)化問題.來自于工業(yè)界的測試用例結(jié)果表明,該算法可以有效地改善合理偏差范圍的分布,而對電路的其它性能影響很小